• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    A pattern according to an embodiment includes first and second line patterns, each of the first and second line patterns extending in a direction intersecting a <111> direction and having a side surface, the side surface having at least one {111} crystal plane, the side surface of the first line pattern has a first roughness and the side surface of the second line pattern has a second roughness that is greater than the first roughness.
    公开号:BE1027584B1
    申请号:E20205155
    申请日:2020-03-06
    公开日:2021-04-16
    发明作者:Susumu Iida；Satoshi Tanaka；Takayuki Uchiyama
    申请人:Kioxia Corp；
    IPC主号:
    专利说明:

    [0001] This application is based on and claims priority from Japanese Patent Application No. 2019-168052 filed on Sep. 17, 2019, the entire contents of which are incorporated herein by reference. AREA
    [0002] The embodiments described here generally relate to a substrate and a method for calibrating a measuring device. BACKGROUND
    [0003] The properties of semiconductor components are strongly influenced by the line edge roughness (LER), i.e. the roughness in the direction of extension of a pattern. In order to calculate the LER based on the measurement with a measuring device such as a CD-SEM, it is necessary to remove the noise of the measuring device by calibration. BRIEF DESCRIPTION OF THE DRAWINGS
    [0004] FIG. 1 is a plan view schematically showing an exemplary configuration of a pattern according to a first embodiment;
    [0005] 2A to 2F are diagrams schematically showing a configuration of a pattern of the sample according to the first embodiment;
    [0006] FIG. 3A and 3B are schematic diagrams showing an example of the flow of a method for manufacturing the pattern according to the first embodiment;
    [0007] FIG. 4 is a schematic diagram illustrating an exemplary configuration of a measuring device according to the first embodiment;
    [0008] FIG. 5 is a block diagram illustrating an exemplary hardware configuration of a control unit of the measuring apparatus according to the first embodiment;
    [0009] FIG. 6A to 6C are diagrams schematically showing the PSD of the LER indicated by the pattern of the sample according to the first embodiment;
    [0010] FIG. 7A to 7C are diagrams each showing an example of actual measurement values of the LER and the correlation length indicated by line patterns of the sample according to the first embodiment and line patterns of a specific sample;
    [0011] FIG. 8A to 8C are diagrams each showing an example of actual measurement values obtained after calibrating the LER and the correlation length and indicated by the line patterns of the sample according to the first embodiment and the line patterns of the specific sample;
    [0012] FIG. 9 is a flowchart showing an example of a method for calibrating a measuring device using the sample according to the first embodiment;
    [0013] FIG. 10 is a plan view schematically showing a configuration of a pattern of a sample according to a first modification of the first embodiment;
    [0014] FIG. 11 is a plan view schematically illustrating a configuration of a pattern of a sample according to a second modification of the first embodiment;
    [0015] FIG. 12 is a schematic diagram illustrating various crystal planes of a particular line pattern;
    [0016] FIG. 13A and 13B are cross-sectional views schematically illustrating an SOI wafer that is a material of a sample according to a second embodiment and a line pattern of the sample;
    [0017] FIG. 14 is a plan view schematically illustrating an exemplary configuration of a sample according to a first modification of the second embodiment;
    [0018] FIG. 15 is a graph illustrating a signal intensity profile of an image obtained from a line pattern according to the first modification of the second embodiment;
    [0019] FIG. 16 is a plan view schematically illustrating an exemplary configuration of a line pattern according to a second modification of the second embodiment;
    [0020] FIG. 17A and 17B are plan views each showing an example of the flow of a line pattern formation method according to a third embodiment; and
    [0021] FIG. 18A and 18B are cross-sectional views illustrating an example of a method for forming a line pattern according to a fourth embodiment. DETAILED DESCRIPTION
    [0022] A pattern according to an embodiment includes first and second line patterns, each of the first and second line patterns extending in a direction intersecting a <111> direction and having a side surface, the side surface having at least one {111} - Has crystal plane, the side surface of the first line pattern has a first roughness and the
    [0023] In the following, the present invention is described in detail with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments. In addition, the components of the following embodiments include components that are readily conceivable or essentially identical to a person skilled in the art.
    [0024] It should be noted that in this specification (hkl) represent a certain crystal plane, {hkl} equivalent crystal planes, and <hkl> equivalent directions.
    [0025] [First Embodiment] In the following, a first embodiment will be described in detail with reference to the drawings.
    [0026] (Exemplary configuration of the pattern) FIG. 1 is a plan view schematically showing an exemplary configuration of a sample 1 according to the first embodiment. The sample 1 is used as a sample for the calibration of a measuring device such as a scanning electron microscope of critical dimensions (CD-SEM).
    [0027] As shown in FIG. As shown in Fig. 1, the sample 1 has a rectangular flat plate, for example. A pattern 10 is arranged on the main surface of the sample 1. The pattern 10 includes a line pattern 11 as a first line pattern, a line pattern 12 as a second line pattern and a line pattern 13 as a third line pattern. Details of this will be described later.
    [0028] The sample 1 is obtained by, for example, cutting a 150 mm or 200 mm silicon substrate with a (110) plane as a main surface into a chip shape.
    [0030] FIG. 2A to 2F are diagrams schematically showing a configuration of a pattern 10 of the sample 1 according to the first embodiment. The FIG. 2A to 2C are plan views of the pattern 10, and FIGS. 2D to 2F are perspective views of the pattern 10.
    [0031] As shown in Figs. 2A to 2F, the line patterns 11 to 13 of the pattern 10 have line and space patterns (LS) each including a plurality of lines. The plurality of lines extend in a direction intersecting a <111> direction which is a crystal orientation of a diamond structure made of silicon. The direction intersecting a <111> direction is, for example, a direction perpendicular to a <111> direction. In addition, the direction that intersects a <111> direction, for example, cannot be completely perpendicular to a <111> direction.
    [0032] More specifically, the line pattern 11 of the line patterns 11 to 13 extends in a direction closest to the direction perpendicular to a <111> direction. The line pattern 12 is rotated clockwise by 0.2 ° with respect to the line pattern 11, for example. The line pattern 13 is rotated, for example, clockwise by 0.4 ° relative to the line pattern 11.
    [0033] The upper surfaces 11t to 13t of the plurality of lines include the (110) plane which is the main surface of the sample 1. The side surfaces 11s to 13s of the plurality of lines in the extending direction each have at least one {111} crystal plane. The line pattern 11 is essentially perpendicular to the <111> direction, and the side surfaces 11s are formed by an essentially single {111} crystal plane. The roughness, i.e., the line edge roughness (LER) of each of the side surfaces 11s of the line pattern 11 is substantially zero.
    [0034] The line pattern 12 is slightly rotated relative to the direction perpendicular to a <111> direction. In this configuration, an atomic step 12a having a crystallographic period appears on each of the side faces 12s of the line pattern 12.
    [0035] Here, the atomic level represents an atomic layer level difference which appears on a crystal surface and has a height of one to several atoms. The height of the atomic level is determined depending on the crystal plane. In the {111} silicon plane, one atomic step with a height of one atom is 3.14 À (about 0.3 nm). A period of the atomic level represents an interval between the atomic levels and differs depending on the degree of deviation between the extending direction of a line pattern and a crystal orientation. When the amount of the deviation is large, the interval between the atomic levels decreases, and when the amount of the difference is small, the interval between the atomic levels increases.
    [0036] The line pattern 12 has a predetermined LER due to the atomic steps 12a that appear periodically on the side surface 12s. For example, in a case where the atomic step 12a has a height of one atom, the line pattern 12 has an LER of 0.3 nm and an LER (30) of 0.9 nm.
    [0037] In comparison to the line pattern 12, the line pattern 13 is rotated further relative to the direction perpendicular to a <111> direction. Therefore, an atomic step 13a appears on each of the side faces 13s of the line pattern 13 with a shorter period than that of the line pattern 12. The line pattern 13 has, for example, the same LER as the line pattern 12. (Method for preparing the sample)
    [0038] Next, a method for producing the sample 1 according to the first embodiment will be described with reference to FIG. 3A and 3B. FIG. 3A and 3B are diagrams showing an example of the procedure for manufacturing the sample 1 according to the first embodiment.
    [0039] As shown in FIG. As shown in FIG. 3A, the condition-setting lines La to Le are formed on a silicon wafer 1w having a (110) plane as a major surface. The lines La to Le are rotated clockwise, e.g. by 0.1 ° relative to an alignment mark MKs as a reference. Lines La to Le also have alignment marks MKa to MKe.
    [0040] These lines La to Le and the alignment marks MKa to MKe and MKs are formed by the formation of a resist pattern, for example by electron beam drawing or the like, and wet etching of the wafer lw to a predetermined depth with an alkaline etching solution, for example a KOH solution, using this resist pattern as a mask.
    [0041] Wet etching with a KOH solution or the like has different wet etching rates depending on the crystal plane. The {111} crystal plane with the slowest wet etching speed appears on the side faces of the
    [0042] It is confirmed whether the line La to Le thus obtained has an extending direction closest to a direction perpendicular to a <111> direction. In other words, it is only necessary to select a line having no atomic level or a line having the least number of atomic levels from the lines La to Le. It is assumed that the line Lb corresponds to this. In this case, the line pattern 11 is formed to have the same rotation angle as the line Lb.
    [0043] As shown in FIG. As shown in FIG. 3B, when the line pattern 11 is formed, a resist pattern corresponding to the alignment mark MKb provided on the line Lb and the alignment mark MKs serving as a reference is formed, and it is wet-etched on the wafer lw.
    [0044] When the line pattern 12 is formed, a resist pattern is formed corresponding to the alignment mark MKd of the line Ld, which is rotated 0.2 ° from the line Lb, and the alignment mark MKs, and wet etching is performed on the wafer lw.
    [0045] When the line pattern 13 is formed, a resist pattern corresponding to the alignment mark of a line which is further rotated by 0.2 ° with respect to the line Ld and the alignment mark MKs is formed and is wet-etched on the wafer lw.
    [0046] Thus, the {111} crystal plane appears on the side surfaces of each of the line patterns 11 to 13. In addition, the atomic steps are formed on the side surfaces according to the rotation angle relative to the direction perpendicular to <111>.
    [0047] As described above, the sample 1 is manufactured according to the first embodiment.
    [0048] (Exemplary Configuration of Measurement Apparatus) Next, an exemplary configuration of a measurement apparatus 200 for calibration with the sample 1 will be described with reference to FIG. 4 and 5. FIG. 4 is a schematic diagram of an exemplary configuration of the measuring device 200 according to the first embodiment. The measuring device 200 is configured as a CD-SEM for measuring, e.g., a critical dimensional shift, LER, and the like of a pattern.
    [0049] As shown in FIG. As shown in FIG. 4, the measuring device 200 includes a lens barrel 211 in which an electron gun 221 is installed as an emission source for the electron beam EB, a sample chamber 212 in which the wafer W is placed, and a control unit 270 configured each unit of the measuring device 200 control.
    [0050] The lens barrel 211 has a cylindrical shape and includes an upper end portion that is closed and a lower end portion that is opened to allow the electron beam EB to pass therethrough. The sample chamber 212 is configured to receive the wafer W. The lens barrel 211 and the sample chamber 212 are combined in an airtight sealed state. The inside of the lens barrel 211 and the sample chamber 212 are configured to be kept at a reduced pressure by a pump or the like, which is not shown.
    [0051] In the lens barrel 211, the electron gun 221, the condenser lenses 231a and 231b, the coils 241a, 241b, 242a and 242b, an objective lens 232 and a detector 251 are installed in this order near the top end portion.
    [0052] The electron gun 221 emits the electron beam EB downward into the lens barrel 211. The electron beam EB emitted from the electron gun 221 moves in the longitudinal axis direction of the lens barrel 211.
    [0053] The condenser lenses 231a and 231b each have an electromagnetic coil concentrically wound around an optical axis of the lens barrel 211, and focus the electron beam EB by a magnetic field.
    [0054] The coils 241a, 241b, 242a, and 242b are a pair of two electromagnetic coils that are configured to deflect the electron beam EB or correct the astigmatism, and that are symmetrically arranged about the optical axis of the lens barrel 211.
    [0055] The objective lens 232 has an electromagnetic coil which is wound concentrically around the optical axis of the lens barrel 211 and which focuses the electron beam EB emitted toward the wafer W by a magnetic field.
    [0056] The detector 251 detects the secondary electrons generated by the wafer W on which the electron beam EB strikes.
    [0057] A wafer table 261 on which a wafer W is placed is installed in the sample chamber 212. An actuator 262 is mounted on the wafer table 261 and configured to move the wafer table 261 back and forth and left and right. Driving the wafer table 261 enables the electron beam EB to be emitted to a predetermined point on the wafer W and incident on the wafer W.
    [0058] The control unit 270 is configured as a computer including a central processing unit (CPU), a random access memory (RAM), a storage device, an I / O port, and the like.
    [0059] FIG. 5 is a block diagram showing an exemplary hardware configuration of the control unit 270 of the measuring device 200 according to the first embodiment.
    [0060] As shown in FIG. 5, the control unit 270 of the measuring device 200 contains a CPU 201, a read-only memory (ROM) 202 as a storage device, RAM 203, a display unit 204, an input unit 205 and an IO port
    [0061] The CPU 201 performs the measurement with the measuring device 200 using various control programs. In addition, the CPU 201 calibrates the measuring device 200 using a calibration program 207 that is a computer program. The calibration program 207 includes a computer program product having a computer readable recording medium that contains a plurality of calibration instructions that can be executed by a computer. In the calibration program 207, the plurality of commands cause the computer to carry out a calibration process of the measuring device 200.
    [0062] The display unit 204 has a display device such as a liquid crystal monitor, and displays a measurement result of the measurement device 200, calibration parameters and the like according to an instruction from the CPU 201. The input unit 205 includes a mouse, a keyboard and the like, and inputs instruction information such as a parameter required for measurement or calibration, which is externally inputted by the user. The command information input to the input unit 205 is transmitted to the CPU 201.
    [0063] The IO port 206 is connected to the electron gun 221, the
    [0064] The CPU 201 controls the electron gun 221, the condenser lenses 231a and 231b, the coils 241a, 241b, 242a and 242b, the objective lens 232, the detector 251, the actuator 262 of the wafer stage 261 and the like through the IO port 206, respectively the content of a control program read from the ROM 202 or the like.
    [0065] The calibration program 207 is stored in the ROM 202 together with the calibration parameters or the like and loaded into the RAM 203 via the bus line. FIG. 5 shows a state in which the calibration program 207 is loaded into the RAM 203.
    [0066] The CPU 201 executes the calibration program 207 loaded into the RAM 203. Specifically, the CPU 201 in the control unit 270 reads the calibration program 207 from the ROM 202 after an instruction entered by the user via the input unit 205, sets the calibration program 207 in a program memory area in the RAM 203 and carries out various calibration processes. The CPU 201 temporarily stores various data generated in the various calibration processes in a data storage area formed in the RAM 203. When each of the calibration processes is completed, the calibration parameters are updated.
    [0067] The calibration program 207 executed by the control unit 270 includes modules, and these modules are loaded onto the main storage device and generated on the main storage device.
    [0068] (Method for calibrating measuring devices).
    [0069] The calibration of the measuring device 200 is carried out for the LER and the correlation length & of a pattern, for example. The correlation length & is an index for how often the same periodic structure is repeated. With respect to the LER of the pattern 10 of the sample 1, the correlation length & corresponds to an interval in which atomic steps occur. Unlike Sample 1, when measuring an actual sample with a random LER, the correlation length & is one of the important parameters, in addition to a value of the LER, and it is also very important to calibrate the correlation length & accurately.
    [0070] Sample 1 is a calibration sample with a predetermined crystal plane and a known LER and correlation length & using atomic steps that appear on the crystal plane. In addition, the LER of sample 1 is very small. The use of such a sample 1 enables the measuring device 200 to be precisely calibrated.
    [0071] The FIG. 6A to 6C are diagrams schematically showing a function of the power spectral density (PSD) of the LER indicated by the pattern 10 of the sample 1 according to the first embodiment. The PSD represents a power distribution of a continuous signal for each frequency band.
    [0072] In each diagram of FIG. 6A to 6C, a horizontal axis shows frequency (f) and a vertical axis shows PSD. In addition, in each of the diagrams, a solid line shows the actual measured values of the sample 10 measured by the measuring device 200 and a broken line indicates an acceptable range of accuracy of the actual measured values. In addition, an alternate long and short broken line in each diagram is a representation of values obtained by removing noise components from an image obtained with the measuring device 200.
    [0073] The correlation lengths & of the LERs of the pattern 10 can be determined, for example, as reciprocal values of the frequencies at points P1 to P3, which are 1 / e lower than the values of the flat areas of the diagrams at low frequencies. Ye "represents the basis of a natural logarithm.
    [0074] As shown in FIG. 6A, the PSD of the line pattern 11 in which the LER is considered zero and the correlation length & is infinite is ideally a delta function. However, since there occurs a noise component resulting from an image of the measuring device 200, the values indicated by the solid line are obtained as actual measured values. The correlation length & obtained from point P1 on the diagram is not infinite.
    [0075] As shown in FIG. 6B, the PSD of the line pattern 12 having the atomic steps occurring with a given period shows a gentler gradient than the PSD of the line pattern 11, and the correlation length & obtained from the point P2 is smaller than that of the line pattern 11.
    [0076] As shown in Fig. 6C, the PSD of the line pattern 13 with the atomic steps appearing with a smaller period shows a gentler gradient than the PSD of the line pattern 12, and the correlation length & obtained from the point P3 is smaller than that of the line pattern 12.
    [0077] FIG. 7A to 7C are diagrams each showing an example of the actual measurement values of the LER and the correlation length & indicated by the line patterns 11 to 13 of the sample 1 according to the first embodiment and the line patterns A to C of a specific sample.
    [0078] FIG. 7A is a diagram of the LER of the line patterns 11 to 13 in which a solid line indicates the actual measured values and a dashed line indicates an acceptable range of accuracy of the actual measured values. In the graphic, the horizontal axis represents line patterns 11 to 13 and the vertical axis represents the LER. FIG. 7B is a graph of the correlation lengths &. the line pattern 11 to 13, in which a solid line indicates the actual measured values and a dashed line an acceptable range of accuracy in the actual measured value. In the diagram, the horizontal axis represents the line patterns 11 to 13 and the vertical axis represents the correlation length &. FIG. 7C is a graph of the LER of the line patterns A through C of a particular sample in which a solid line indicates the actual measurement value and a dashed line indicates an acceptable range of accuracy in the actual measurement value. In the diagram, the horizontal axis of the diagram represents line patterns A through C and the vertical axis represents the LER.
    [0079] In the examples of FIG. 7A and 7B, the actual measured values of the LER and the correlation lengths & of the line patterns 12 and 13 are within the acceptable range. However, the actual measured values of the two LERs and the correlation length & of the line pattern 11 are outside the acceptable range. In other words, in the examples of FIG. 7A and 7B it can be seen that the measuring device 200 has to correct the measured value when the
    [0080] In such a state, when the LER of the line patterns A to C of an actual sample that is the specific sample are measured, the actual measurement value of the line pattern A having a smaller LER is also out of the acceptable range as shown in FIG. 7C.
    [0081] FIG. 8A to 8C are diagrams each showing an example of actual measurement values obtained after calibrating the LER and the correlation length & by the line patterns 11 to 13 of the sample 1 according to the first embodiment and the line patterns A to C of the specific sample are displayed.
    [0082] FIG. 8A is a diagram of the LER of the line patterns 11 to 13 in which a solid line indicates the actual measured values of the measuring device 200 after calibration and a dashed line indicates an acceptable range of accuracy of the actual measured values. In the graph, the horizontal axis represents the line patterns 11 to 13 and the vertical axis represents the LER. FIG. 8B is a diagram of the correlation lengths & the line patterns 11 to 13, in which a solid line indicates the actual measured values of the measuring device 200 after calibration and a dashed line indicates an acceptable range of accuracy in the actual measured value. In the diagram, the horizontal axis represents the line patterns 11 to 13 and the vertical axis represents the correlation length &. FIG. 8C is a diagram of the LERs of the line patterns A to C of the particular sample, in which a solid line indicates the actual measurement value and a dashed line indicates an acceptable range of accuracy in the actual measurement value. In the diagram, the horizontal axis of the diagram represents the
    [0083] As shown in FIGS. As shown in Figures 8A and 8B, all of the graphs of the line patterns 11-13 are within the acceptable range. The calibration using the sample 1 with a known LER and correlation length & enables the subsequent high-precision measurement of a sample with an unknown and random LER and correlation length & in the measuring device 200, as shown in FIG. 8C.
    [0084] It should be noted that in FIGS. 7A to 7C show the examples in which, with decreasing LER and increasing correlation length &, the actual measured values measured by the measuring device 200 deviate, but the tendency towards the deviation of the actual measured values measured by the measuring device, which is recognizable after sample 1, is not limited to this example. In some measuring devices, for example, an actual measurement value may differ with increasing LER or decreasing correlation length &, or an actual measurement value with respect to a certain LER and correlation length &, and the use of the sample 1 enables such a tendency to be understood.
    [0085] FIG. 9 is a flowchart showing an example of a procedure of the method for calibrating the measuring device 200 using the sample 1 according to the first embodiment.
    [0086] As shown in FIG. 9, each of the line patterns 11 to 13 of the sample 1 is measured with the measuring device 200 to acquire the actual measured values of the LER and the correlation length & (step S101).
    [0087] It is determined whether the obtained actual measurement values have an accuracy within an acceptable range (step S102).
    [0088] If an actual measurement value does not have an accuracy within the acceptable range (step S102: No), the measuring device 200 is calibrated (step S103).
    [0089] After the calibration of the measuring device 200, the line patterns 11 to 13 of the sample 1 are measured again in order to acquire the actual measured values of the LER and the correlation length (step S104).
    [0090] It is determined whether the obtained actual measurement values have an accuracy within an acceptable range (step S102). If the actual measurement values have an accuracy within the acceptable range (step S102: Yes), the process is ended.
    [0091] This is the end of the calibration of the measuring device 200 using the sample 1 according to the first embodiment.
    [0092] (Comparative Example) The LER measured with a measuring device such as CD-SEM tends to be large due to the influence of noise. Therefore, as the configuration of the comparative example, there has been proposed a calculation method in which a noise component is subtracted with software by calibrating the measuring device.
    [0093] However, there is no standard calculation method, and even if the measurement is made with the same sample, the values of LER and correlation length & are different.
    [0094] In microfabrication by means of optical
    [0095] The sample 1 according to the first embodiment includes the line patterns 11 to 13 which extend in a direction intersecting a <111> direction and which have side faces with at least one {111} crystal plane in the extending direction. Thus, sample 1 with a known LER and correlation length & can be obtained.
    [0096] The sample 1 according to the first embodiment is used by fitting into wafers W of various sizes. The sample 1 can thus be used jointly for different measuring devices 200. Therefore, these measuring devices 200 can be calibrated in each of the different measuring devices 200 in order to obtain the same measurement result for the same sample.
    [0097] Note that the sample 1 according to the first embodiment has a chip shape and is used by fitting into the wafer W, but the sample 1 is not limited to this. The wafer 1w on which the pattern 10 has been formed can be used directly for the measurement by the measuring device 200 and the calibration of the measuring device 200 without being cut into chips.
    [0098] Furthermore, as described above, the atomic step can have a height of one to several atoms, and adjusting the number of atoms making up the height of the atomic step enables various LERSs to be measured. As described above, when the atomic level is one atom in height, the LER is 0.3 nm (LER (30) is 0.9 nm). The atomic step with a height of two atoms has a step difference of 6.28 À, and the LER is 0.6 nm (LER (30) is 1.8 nm).
    [0099] The number of atoms composing the atomic level can be increased by increasing the angle of rotation of the line pattern. In other words: as the deviation from a direction orthogonal to a <111> direction increases, an atomic step tends to have a large step difference. This can also reduce the interval between the atomic levels, i.e. the correlation length &.
    [9100] [9100] The step difference of the atomic step and an interval between the atomic steps can also be controlled as a function of an etching solution, wet etching conditions or the like.
    [0101] In addition, a wafer with a (110) plane as the main surface and as the material of a sample can be a wafer which, in addition to silicon, also has a multi-element crystal that has a zincblendic crystal structure such as GaAs or GaSn. For example, GaAs has a lattice spacing slightly different from that of silicon, and GaAs has a spacing between {111} crystal planes of 3.26 À, which is slightly larger than that of silicon. The size of the LER can therefore be controlled through the different selection of a material for the wafer.
    [0102] (First Modification) Next, a sample 2 according to a first modification of the first embodiment will be described with reference to FIG. 10 described. FIG. 10 is a plan view schematically showing a configuration of a pattern 20 of the sample 2 according to the first modification of the first embodiment. The sample 2 according to the first modification differs from the sample 1 according to the first embodiment described above in that the period of the LER is random.
    [0103] As shown in FIG. As shown in FIG. 10, the sample 2 has a major surface that is a (110) plane, and the pattern 20 is disposed on the major surface. The pattern 20 includes a line pattern 21 as a first line pattern, a line pattern 22 as a second line pattern and a line pattern 23 as a third line pattern.
    [0104] The line patterns 21 to 23 extend in a direction that is substantially perpendicular to a <111> direction. In other words, a basic pattern of the line patterns 21 to 23 is configured similarly to the line pattern 11 according to the first embodiment, with an LER of substantially zero and a correlation length & that is basically infinite.
    [0105] On the basis of such a line pattern, the LER is introduced into the line patterns 22 and 23 with a random period. Such line patterns 22 and 23 can be formed by roughening minute irregularities 22c and 23c on the side surfaces of the line patterns 22 and 23, for example, by ashing, dry etching or the like.
    [0106] In addition, the line pattern 23 has a larger LER than the line pattern 22. The LER is adjustable by changing the conditions for ashing or dry etching. For example, in a case where ashing is applied, a larger LER can be achieved by increasing the plasma generation voltage or by increasing the processing time. In a case where dry etching is used, in addition to the above method, another LER can be obtained by selectively etching with a resist pattern with a predetermined LER as a mask.
    [0107] For example, in order to know the LER and correlation lengths & of the line patterns 22 and 23, it is preferable to form dummy patterns in advance according to the ashing or dry etching conditions to be used, the dummy patterns or the like with a transmission electron microscope (TEM) or the like observe and record the values of the LER and correlation lengths &.
    [0108] It should be noted that the line pattern 21 is not subjected to ashing, dry etching or the like and has an initial mirror surface.
    [0109] (Second Modification) Next, a sample 3 according to a second modification of the first embodiment will be described with reference to FIG. 11 described. FIG. 11 is a plan view schematically showing a configuration of a pattern 30 of the sample 3 according to the second modification of the first embodiment. The sample 3 according to the second modification differs from the sample 2 according to the above-described first modification in a method for introducing LER.
    [0110] As shown in FIG. 11, the pattern 3 has a main surface which is a (110) plane, and the pattern 30 is disposed on the main surface. The pattern 30 includes a line pattern 31 as a first line pattern, a line pattern 32 as a second line pattern, and a line pattern 33 as a third line pattern.
    [0111] The line patterns 31 to 33 extend in a direction that is substantially perpendicular to a <111> direction. In other words, a basic pattern of the line patterns 31 to 33 is configured similarly to the line pattern 11 according to the first embodiment described above, with an LER of substantially zero and a correlation length & that is basically infinite.
    [0112] On the basis of such a line pattern, the LER with a random period is introduced into the line patterns 32 and 33 using the particles 32p and 33p. In other words, the particles 32p and 33p with known particle sizes are appended to the line patterns 32 and 33, respectively. It is assumed that a particle 33p attached to the line pattern 33 has a larger particle size than a particle 32p attached to the line pattern 32.
    [0113] It should be noted that the line pattern 31 has no particles and has an initial mirror surface.
    [0114] [0114] [Second Embodiment] In the following, a second embodiment will be described in detail with reference to the drawings. The second embodiment differs from the above-described first embodiment in the configuration in which a silicon-on-insulator (SOI) wafer, which is a material of a sample, is used as a substrate.
    [0115] FIG. 12 is a schematic diagram illustrating various crystal planes of a particular line pattern 40. The line pattern 40 has lines extending in a direction substantially perpendicular to a <111> direction on a substrate having a (110) plane as a major surface.
    [0116] As shown in FIG. 12, the line pattern 40 has a side surface 42 with a {111} crystal plane that is substantially perpendicular to an upper surface 41 with the (110) plane, and a foot portion 44 that connects to a connecting portion with a lower surface 43 is arranged with the (110) -plane. The foot portion 44 has another {111} crystal plane that appears when the line pattern 40 is formed (reference: Micro- and Nano Engineering 3 (2019) 44-49). The {111} crystal plane of the foot section 44 has a different angle than the {111} crystal plane of the side surface 42.
    [0117] When, for example, a measurement is carried out with the measuring device 200 or the like, or when a microscope has a large depth of field, an inclined {111} crystal plane, such as the foot section 44 described above, can represent the contour of the line pattern 40 in an image blur.
    [0118] The configuration of the second embodiment described below suppresses the formation of the {111} inclined crystal plane.
    [0119] (Method for preparing the sample) FIG. 13A and 13B are cross-sectional views schematically showing an SOI wafer Sw as a material of a sample according to the second embodiment and a line pattern 51 of the sample.
    [0120] As shown in FIG. 13A, the SOI wafer 5w includes a substrate 50sb with silicon or the like, a box layer 50bx with an insulating layer such as a silicon oxide layer, and an active layer 50ac with a silicon layer or the like.
    [0121] The active layer 50ac has a crystal structure with a (110) plane as a major surface. In a case where the SOI wafer is manufactured e.g. by separation by an oxygen implantation method (SIMOX), the substrate 50sb also has a (110) crystal plane. In a case where the substrate 50sb has (110) crystal, it is advantageous that processing such as cleavage is facilitated.
    [0122] However, the substrate 50sb does not necessarily have one
    [0123] The line pattern 51 can be obtained by forming lines in the active layer 50ac of the SOI wafer 5w.
    [0124] As shown in FIG. 13B, the line pattern 51 as the first line pattern has a line and space pattern in which a lower surface 51b reaches the box layer 50bx. For example, the line pattern 51 extends in a direction substantially perpendicular to a <110> direction that is a crystal orientation of the active layer 50ac.
    [0125] In wet etching with a KOH solution or the like, the box layer 50bx such as a silicon oxide layer is hardly etched relative to the active layer 50ac such as silicon and has a high selectivity. If wet etching is continued using this high selectivity until a sloped surface like that shown in FIG. 12 of the foot portion 44 disappears, the line pattern 51 without the inclined surface can be obtained.
    [0126] It is possible to apply the configurations of the first embodiment and the first and second modifications described above to a sample having such an SOI wafer 5w. In other words, if, based on the line pattern 51, second and third line patterns are formed which extend in a direction that is intentionally shifted from a direction perpendicular to the <110> direction, a sample corresponding to the above-mentioned sample according to FIG first embodiment can be obtained. In addition, when the second and third line patterns having a side surface roughened by dry etching or the like are formed on the basis of the line pattern 51, a pattern corresponding to the above-mentioned pattern according to the first modification of the first embodiment can be obtained. In addition, when forming the second and third line patterns to which particles of known particle size are attached, based on the line pattern 51, a sample corresponding to the above-mentioned sample according to the second modification of the first embodiment can be obtained.
    [0127] It should be noted that the thickness of the active layer may be set differently depending on the conditions for manufacturing the SOI wafer, polishing after manufacturing, or the like. A line pattern can be formed by combined dry and wet etching using an SOI wafer with a thick active layer.
    [0128] The dry etching is excellent for forming a deep groove with high verticality. However, a complete crystal plane does not appear on the dry-etched surface. In wet etching using a KOH solution or the like, a processed surface has a substantially entire crystal plane, but the wet etching is an isotropic etching and is not capable of forming a pattern with a small slope.
    [0129] Therefore, dry etching is used for deep etching the SOI wafer from the thick active layer to a box layer, and then wet etching is performed using a KOH solution or the like, thereby shortening the processing time of the wet etching and increasing the Slope of the line pattern can be prevented. Therefore, the line pattern with a small slope with a {111} -
    [0130] In a case where the line pattern is formed with a small slope, a method such as metal-assisted chemical etching (MacEtch), which is excellent in processing a pattern having a higher aspect ratio, can be used.
    [0131] (First Modification) Next, a sample 6 according to a first modification of the second embodiment is described with reference to FIG. 14 and 15. The sample 6 according to the first modification differs from the sample according to the second embodiment described above in that the sample 6 contains the line patterns 6la to 63a and 61f to 63f with different electrical states.
    [0132] FIG. 14 is a plan view schematically illustrating an exemplary configuration of the sample 6 according to the first modification of the second embodiment. As in FIG. 14, the sample 6 according to the first modification also has an SOI wafer and contains a pattern 60 arranged on a box layer 60bx. The pattern 60 includes the line patterns 6la to 63a and 61f to 63 £.
    [0133] The line patterns 6la and 61f as first line patterns extend in a direction substantially perpendicular to a <110> direction and have an LER which can be regarded as substantially zero and a substantially infinite correlation length &. A LER having a predetermined correlation length & is introduced into the line patterns 62a and 62f as a second line pattern and the line patterns 63a and 63f as a third line pattern by at least one of the methods in the first embodiment and its first and second modifications described above .
    [0134] The line patterns 61f to 63f are arranged on the box layer 60bx as an insulating layer which is in a floating state. The line patterns 6la to 63a are connected to a ground wire 64 which is in a grounded state. This configuration enables the influence of the charge by an electron beam from a measuring device on the measuring accuracy to be examined.
    [0135] However, the line patterns 61a to 63a may be grounded by a method other than the above-described method. For example, the line patterns 6a to 63a can be brought into the grounded state by bringing them into physical contact with an SOI wafer substrate. In addition, if the line patterns 61a to 63a each have a sufficiently large volume, their electric capacity increases and an influence of charging can be neglected.
    [0136] FIG. 15 is a graph illustrating the signal intensity profiles of images obtained from the line patterns 61a and 61f according to the first modification of the second embodiment. In the graph, the horizontal axis represents the measurement position in a cross section in a direction perpendicular to an extending direction of each of the line patterns 61a and 61f, and the vertical axis represents the signal intensity.
    [0137] As shown in FIG. 15, a line width of the line pattern 61f charged in the floating state is measured to be wider than a line width of the line pattern 6la in the grounded state (reference: Journal of Vacuum Science & Technology B36, 06J502 (2018)). When the uncharged line patterns 61a and 61f are measured, their signal intensity profiles are almost the same, and it is known
    [0138] The sample 6 according to the first modification of the second embodiment makes it possible to show the accuracy and precision in the result of measurement of the pattern under the influence of charging, and also makes it possible to evaluate a technique of charging countermeasure in the measuring device.
    [0139] (Second Modification) It is also possible to apply the configurations of the above-described second embodiment and the first modification of the second embodiment to a sample for calibrating a defect inspection device.
    [0140] In the defect inspection apparatus, a pattern into which a defect, a so-called programmed defect, is introduced can be evaluated to determine whether a defect of a predetermined size is correctly recognized, the programmed defect being a needle point defect, a Has a pinhole defect or the like which is a target to be recognized by the defect inspection device and has an intentionally changed size. A determination result is used to calibrate the defect inspection device.
    [0141] However, if the pattern used for the determination has an LER greater than or equal to a predetermined size, the pattern becomes a disruptive factor in the evaluation in the defect inspection device.
    [0142] Therefore, as shown in FIG. 16, a line pattern 61ie with no programmed defect and a line pattern 65ie in which a programmed defect 65p is introduced are formed based on the line pattern 51 according to the second embodiment, and the evaluation of the defect inspection apparatus can be performed in such a state that the LER as a disturbance factor is essentially zero. In addition, in a case where the programmed defect 65p is introduced, the influence of the LER need not be considered, and the programmed defect 65p can be set to a minute size of, for example, about 2 nm or less.
    [0143] In addition, in forming a line pattern with no programmed defect and a line pattern into which a programmed defect is introduced, based on the line patterns 61a and 61f according to the first modification described above, the influence of charging on the defect inspection device can also be examined.
    [0144] [0144] [Third Embodiment] In the following, a third embodiment will be described in detail with reference to the drawings. The third embodiment differs from the first and second embodiments in a configuration in which a line pattern with a predetermined crystal plane is formed on a side wall by crystal growth.
    [0145] (Method for preparing the sample) FIG. 17A and 17B are plane views each showing an example of the flow of a method for forming a line pattern 71 according to a third embodiment.
    [0146] FIG. 17A illustrates a line pattern 71p formed by a lithography technique such as optical lithography or electron beam lithography and a dry etching technique such as reactive ion etching (RIE). The line pattern 71p extends in a direction substantially perpendicular to a <110> direction.
    [0147] As shown in FIG. 17A, the line pattern 71p formed by lithography and dry etching may have an increased LER caused by irregularities 71c formed on a side surface by, for example, transferring an LER of a resist pattern or a side wall roughness by dry etching.
    [0148] Next, a protective layer (not shown) including an insulating layer or the like is formed on an upper surface of the line pattern 71p. When the line pattern 71p is formed, a hard mask for supporting a resist pattern or the like may be formed in advance so that the hard mask can be used as a protective layer.
    [0149] Next, crystal growth is performed on the line pattern 71p using a liquid phase growth technique or the like. In the liquid phase growth technique, crystal growth proceeds in a state close to the equilibrium state, so that a {111} crystal plane, which is the most stable plane, can be easily formed. The crystal growth is hardly performed on the top of the line pattern 71p due to the presence of the protective layer.
    [0150] In addition, by setting a temperature of a solution or melt, both etching and dissolving or melting and crystal growth are carried out in parallel. Thereby, it is possible to perform crystal growth mainly on one side surface of the line pattern 71p while suppressing the increase in the line width of the line pattern 71p.
    [0151] Specifically, first, the etching is advanced by a slight increase in the temperature of the solution or melt relative to its equilibrium temperature. At this time, an area having a small radius of curvature such as the irregularities 71c on the side surface of the line pattern 71p is preferably etched. Then the crystal growth is promoted by lowering the temperature of the solution or melt, so that the line width is not reduced too much.
    [0152] When the side surface of the line pattern 71p is substantially completely covered with the {111} crystal plane, the liquid phase growth is finished. Thereafter, the protective layer, which is not shown, is removed from the upper surface of the line pattern 71p.
    [0153] FIG. 17B shows the line pattern 71 as a first line pattern obtained as described above. The line pattern 71 includes a side face 71s with a {111} crystal plane and has an LER which can be regarded as substantially zero and a substantially infinite correlation length &.
    [0154] When second and third line patterns into which an LER having a predetermined correlation length & is introduced are formed on the basis of the line pattern 71 by at least one of the above-described methods according to the first embodiment and the first and second modifications thereof, a Sample can be obtained according to the third embodiment.
    [0155] Note that, for example, in the processing with the lithography technique and the dry etching technique, it is possible to make a fine pattern with a half pitch of 20 nm or less. An electron beam, for example, is preferably used to produce the fine pattern.
    [0156] The sample according to the third embodiment makes it possible to show the accuracy and precision of a measurement result such as the line pattern 71 with a fine half pitch of 20 nm or less. By using this for the calibration of the measuring device, the measuring accuracy in a fine pattern can be improved.
    [0157] It should be noted that, as the material of the sample according to the third embodiment, both a silicon wafer and an SOI wafer can be used.
    [0158] (Modification) As a modification, in place of the liquid phase growth technique in the third embodiment, a vapor phase growth technique such as molecular beam epitaxy (MBE) or organometallic chemical vapor deposition (MOCVD) can also be used.
    [0159] In the vapor phase growth technique, the crystal growth rate is slower than in the liquid phase growth technique, and the line width can be easily controlled. In addition, not only a {111} crystal plane as the most stable plane but also a metastable plane such as a {110} crystal plane or a {100} crystal plane can be formed depending on the crystal growth conditions. A obtained crystal plane also depends strongly on the crystal orientation of a base for crystal growth. With this property, exposure of a (110) plane which is an upper surface of a line pattern after dry etching results in a state in which the (110) plane slightly on the upper surface and the {111} crystal plane slightly one side surface grows.
    [0160] In addition, when using the vapor phase growth technique, it is preferable to reduce the line width of the line pattern beforehand after dry etching. A negative resist is often used for electron beam lithography or extreme ultraviolet (EUV) lithography. In this case, it is easy to make a line width narrower than a room width. Thus, even if the line width is increased by vapor phase growth, a line pattern having a desired line width can be obtained.
    [0161] Depending on the modification, both a silicon wafer and an SOI wafer can be used as the material of a sample.
    [0162] Fourth Embodiment In the following, a fourth embodiment will be described in detail with reference to the drawings. The fourth embodiment differs from the first to third embodiments described above in a configuration having a finer line pattern.
    [0163] (Method for preparing the sample).
    [0164] As shown in FIG. As shown in Fig. 18A, for example, a mask pattern 80ox such as a silicon oxide film is formed on a wafer 8w having a (110) plane as a main surface. The mask pattern 80ox is formed so as to extend in a direction substantially perpendicular to a <110> direction of the wafer 8w.
    [0165] For the formation of the mask pattern 80o0x, for example, a hydrogen silsesquioxane (HSQ) resist, which is a negative electron beam resist, can be used.
    [0166] The HSQ resist is a resist based on silicon and is converted into SiO 2 by annealing after structuring. The structuring of the HSO resist is done e.g. by electron beam lithography. By using the HSQ resist, a fine mask pattern 80ox such as a silicon oxide film can be obtained relatively easily.
    [0167] Next, crystal growth is performed on the wafer 8w on which the mask pattern 80ox is formed using a liquid phase growth technique or a vapor phase growth technique. The crystal is selectively grown on the (110) plane of the wafer 8w exposed from the mask pattern 80ox. When an upper surface of the crystal exceeds the height of the mask pattern 80ox, the crystal also slightly expands laterally. At this time, the top surface of the crystal has the (110) plane which coincides with the main surface of the wafer 8w as a base. A side face of the crystal has a {111} crystal plane, which is the most stable plane. It should be noted that when the liquid phase growth technique is used, the {111} crystal plane may be formed on the top surface of the crystal. In such a case, the top surface of the crystal is flattened by a chemical mechanical polishing (CMP) process.
    [0168] FIG. 18B illustrates the line pattern 81 as a first line pattern obtained as described above. The line pattern 81 includes a crystal 80gr obtained by crystal growth, has a side face 81s with a {111} crystal plane and an LER which can be regarded as substantially zero, and a substantially infinite correlation length 65.
    [0169] When second and third line patterns into which an LER having a predetermined correlation length & is introduced are formed based on the line pattern 81 by at least one of the above-described methods according to the first embodiment and the first and second modifications thereof, and a Sample can be obtained according to the fourth embodiment.
    [0170] In the above description, in forming the second and third line patterns extending in a direction intentionally shifted from a direction perpendicular to the <110> direction based on the line pattern 81, the (110) - The plane of the main surface of the wafer 8w becomes a seed crystal. Therefore, the side face of the crystal growing therefrom has the {111} crystal plane, and an atomic step with a crystallographic period is formed.
    [0171] Note that, as the material of the sample according to the fourth embodiment, both a silicon wafer and an SOI wafer can be used.
    [0172] Incidentally, as in the third and fourth embodiments described above, it is also possible to introduce a programmed defect in the line patterns 71 and 81 obtained by using crystal growth to prepare a sample for calibration of the defect inspection device. For example, when the programmed defect is formed only by etching, a high-index plane appears on a side surface of the programmed defect, thereby increasing the etching rate, and it is difficult to control the size of the programmed defect. As described above, when the crystal growth is used, it is possible to form a {111} crystal plane on a side face of a programmed defect, and control of the size of the programmed defect is facilitated.
    [0173] While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein can be embodied in a variety of other forms; in addition, various omissions, substitutions, and modifications can be made in the form of the embodiments described herein without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications that would come within the scope and spirit of the inventions.
    权利要求:
    Claims (20)
    [1]
    A substrate comprising: first and second line patterns extending in directions intersecting a <111> direction and having at least one {111} crystal plane on each of the side faces, the side face of the first line pattern being a first Has roughness and the side surface of the second line pattern has a second roughness that is greater than the first roughness.
    [2]
    2. The substrate of claim 1, wherein the first line pattern extends in a first direction closer to a direction perpendicular to a <111> direction relative to the second line pattern, and the second line pattern extends in a second direction oblique to the direction of extension of the first Line pattern extends, wherein the side surface of the second line pattern has an atomic step that appears with a first period.
    [3]
    3. The substrate of claim 1, wherein the side surface of the first line pattern has a mirror surface and the side surface of the second line pattern has random irregularities.
    [4]
    4. The substrate of claim 1, wherein a particle having a first diameter is attached to the side surface of the second line pattern.
    [5]
    5. The substrate of claim 1, wherein the second roughness of the side surface of the second line pattern is achieved by introducing a programmed defect on the side surface of the second line pattern having the first roughness.
    [6]
    6. The substrate according to claim 1, wherein the first and second line patterns are arranged on a substrate having a (110) plane as a major surface, and an upper surface of the first and second line patterns includes the major surface of the substrate.
    [7]
    7. The substrate according to claim 1, wherein the first and second line patterns are arranged on a substrate having a (110) plane as a main surface, and a lower surface of the first and second line patterns is in contact with the main surface of the substrate, respectively.
    [8]
    8. The substrate of claim 7, wherein an insulating layer covering a part of the substrate is disposed on the substrate, and the first and second line patterns are disposed on the substrate exposed from the insulating layer.
    [9]
    9. The substrate of claim 1, wherein the first and second line patterns are arranged on an insulating layer.
    [10]
    10. The substrate of claim 9, wherein part of the first and second line patterns are in a floating state and the other part of the first and second line patterns are in a grounded state.
    [11]
    11. A method of calibrating a measuring device, comprising: measuring the first and second line patterns of a sample by the measuring device; and calibrating the measuring device based on a measurement result, the sample including the first and second line patterns extending in directions intersecting a <111> direction and having at least one {111} crystal plane on each of the side faces, wherein the side surface of the first line pattern has a first roughness and the side surface of the second line pattern has a second roughness that is greater than the first roughness.
    [12]
    12. The method of calibrating the measuring device according to claim 11, wherein the first line pattern extends in a first direction closer to a direction perpendicular to a <111> direction relative to the second line pattern, and the second line pattern extends obliquely in a second direction extends to the direction of extension of the first line pattern, wherein the side surface of the second line pattern has an atomic step that appears with a first period.
    [13]
    13. The method for calibrating the measuring device according to claim 11, wherein ai BE2020 / 5155 the side surface of the first line pattern has a mirror surface and the side surface of the second line pattern has random irregularities.
    [14]
    14. The method of calibrating the measuring device according to claim 11, wherein a particle having a first diameter is attached to the side surface of the second line pattern.
    [15]
    15. The method for calibrating the measuring device according to claim 11, wherein the second roughness of the side surface of the second line pattern is achieved by performing a programmed defect on the side surface of the second line pattern having the first roughness.
    [16]
    16. The method of calibrating the measuring device according to claim 11, wherein the first and second line patterns are arranged on a substrate having a (110) plane as a main surface, and an upper surface of the first and second line patterns includes the main surface of the substrate.
    [17]
    17. The method for calibrating the measuring device according to claim 11, wherein the first and second line patterns are arranged on a substrate having a (110) plane as a main surface, and a lower surface of the first and second line patterns each with the main surface of the substrate is in contact.
    [18]
    18. The method of calibrating the measuring device according to claim 17, wherein an insulating layer covering a part of the substrate is arranged on the substrate, and the first and second line patterns are arranged on the substrate exposed from the insulating layer.
    [19]
    19. The method for calibrating the measuring device according to claim 11, wherein the first and second line patterns are arranged on an insulating layer.
    [20]
    20. The method of calibrating the measuring device according to claim 19, wherein part of the first and second line patterns are in a floating state and the other part of the first and second line patterns are in a grounded state.
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    同族专利:
    公开号 | 公开日
    JP2021048156A|2021-03-25|
    TW202114132A|2021-04-01|
    BE1027584A1|2021-04-09|
    CN112525116A|2021-03-19|
    US20210082662A1|2021-03-18|
    TWI742525B|2021-10-11|
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    法律状态:
    2021-05-26| FG| Patent granted|Effective date: 20210416 |
    优先权:
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    JP2019168052A|JP2021048156A|2019-09-17|2019-09-17|Substrate, pattern, and calibration method of measurement device|
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